We are pleased to feature Prof. Yuqing Jiao, Associate Professor at Eindhoven University of Technology (TU/e), as the second distinguished guest in the Asia Photonics Expo (APE) Photonics Spotlight Series.
In this insightful interview, Prof. Jiao provides in-depth perspectives on the current challenges and future trajectory of heterogeneous integration, the evolving role of nanophotonics in advancing quantum technologies, and the principal bottlenecks limiting large-scale photonic integrated circuit (PIC) manufacturing. He further outlines strategic approaches for reinforcing Europe’s leadership in photonics and offers his view on how the Asia Photonics Expo can play an increasingly pivotal role in driving global collaboration.
Join us as we examine the critical issues and emerging opportunities shaping the next era of photonics innovation.
Q: TU/e is internationally recognised as a leader in heterogeneous integration platforms for photonic integrated circuits. As AI computing accelerates and the demand for optical interconnects in data centers continues to rise, what do you see as the key challenges that InP–Si heterogeneous integration must still overcome to achieve high-speed optoelectronic conversion and improved power efficiency?
Additionally, in the context of emerging co-packaged optics (CPO) architectures, how can heterogeneous integration strike an effective balance between performance, cost, and manufacturing complexity?
A: Heterogeneous integration enables the combination of materials optimised for specific functions—such as InP for light generation, Si or SiN for routing, and Ge or InGaAs for detection—on a single monolithic platform. In principle, this approach can outperform any single-material technology. However, several challenges must still be addressed before it can become the dominant solution for high-speed, energy-efficient CPO systems.
One critical issue is thermal and reliability management. Bonding and transfer processes introduce additional thermal cycles, interfaces (such as InP–SiO₂–Si), and complex chemical steps. The long-term impact of these factors on device performance, yield, and heat dissipation remains insufficiently understood, and further research is required to establish robust reliability models.
A second challenge relates specifically to CPO architectures, where the industry has yet to define an optimal boundary between what should be heterogeneously integrated and what should remain within the package. While heterogeneous integration offers the promise of wafer-scale manufacturability and, over time, lower cost and improved scalability, it is still less mature than established packaging technologies. Conversely, conventional packaging is far more mature today but is beginning to approach fundamental performance and cost limits at extreme data rates.
Given this landscape, a hybrid strategy is likely the most pragmatic path forward: heterogeneously integrates only the high-performance or high-density building blocks where speed, bandwidth, or scaling critically depend on monolithic integration, while retaining the rest within the package to leverage existing maturity and simplify manufacturing. This balances performance, cost, and complexity in a realistic and evolutionary way.
Prof. Yuqing Jiao, Associate Professor at Eindhoven University of Technology (TU/e)
Q: As photonic integrated circuits (PICs) move from laboratory prototypes to large-scale commercial production, they face manufacturing challenges that differ significantly from those of electronic chips. In your view, what are the most critical bottlenecks currently limiting large-scale PIC manufacturing — material uniformity, process tolerance, testing and packaging, or other factors?
A: Photonic devices operate in an analogue domain, and photons are highly sensitive to nanometer-scale deviations. As a result, any material or process non-uniformity can directly translate into wavelength shifts, insertion-loss variations, and coupling inefficiencies. These are significant challenges, but importantly, they are not fundamental bottlenecks—they are engineering issues that can be resolved as the supply chain gets more investment. The contrast between Si and InP industries illustrates this well — silicon foundries achieve exceptional uniformity because of decades of market-driven investment, while InP lags primarily due to a relatively smaller market rather than any inherent material limitation. As the demand for PICs increases, I expect similar improvements in III–V and heterogeneous platforms.
Testing, however, remains one of the most critical barriers, especially at the wafer level. The wafer-level testing is crucial for early identification of defective devices or dies before dicing or heterogeneous integration, yet it is intrinsically difficult because PICs are designed to keep light tightly confined. Surface grating couplers, micro-mirrors, and other optical test structures allow limited device-level probing, but they are not yet optimised for massive parallelism or high-throughput industrial workflows. Significant effort is still required to standardise wafer-level optical I/O, develop scalable probing architectures, and integrate design-for-test concepts so that large-scale PIC manufacturing can reach semiconductor-grade efficiency.
Q: Heterogeneous integration is a key enabler in the post-Moore era, combining materials such as silicon, lithium niobate, and indium phosphide to achieve functionalities unattainable in a single platform. From your perspective, what are the principal challenges in realising low-loss, reliable, and scalable interfaces across these diverse material systems? Additionally, what emerging techniques or innovations show the most promise in overcoming these integration barriers?
A: When integrating materials with completely different thermal expansion coefficients, mechanical stress inevitably concentrates at their interfaces. In photonics, this challenge is further compounded by the use of thick dielectric buffer layers such as SiO₂ which isolates InP photonic layers from a Si substrate and prevents optical leakage, introducing additional mechanical and thermal constraints. These multi-material stacks undergo several post-processing temperature cycles, and any mismatch in expansion or heat dissipation can lead to warping, delamination, or long-term reliability issues, ultimately affecting device yield. Furthermore, heterogeneous photonic interfaces demand exceptionally high surface quality, as even sub-nanometer non-flatness or a single contaminant particle can lead to bonding failure.
Several emerging techniques are addressing these challenges. Micro-transfer printing allows “known-good” III–V or lithium niobate dies to be placed selectively, avoiding bad components identified by on-wafer testing and significantly improving system-level yield. Another promising development is room-temperature plasma-activated bonding, which achieves permanent wafer-scale bonds without the 200–400 °C thermal budget of conventional bonding. By eliminating high-temperature stress and reducing the risk of material degradation, it improves both yield and long-term reliability. Collectively, these advances represent a new generation of integration techniques that make heterogeneous Si–InP–LN platforms increasingly scalable, robust, and suitable for high-performance photonic applications.
Q: Nanophotonics is increasingly recognised as a critical enabler for quantum information processing. Drawing on your expertise in nanofabrication, how do you evaluate the potential of silicon-based nanophotonic platforms to advance qubit control, generate quantum entanglement, and support the development of scalable quantum networks?
A: I view silicon-based nanophotonics as an excellent foundational platform for quantum photonics. It benefits from CMOS-compatible fabrication, dense waveguide integration, and mature design libraries, and we have seen impressive demonstrations of on-chip entangled photon-pair generation, multi-photon interference, and large-scale reconfigurable quantum processors on Si/SiN.
From a nanofabrication perspective, its ultimate potential depends on achieving consistently “quantum-grade” process control—sub-dB/cm propagation loss, ultra-stable phase stability across large interferometer meshes, and reproducible coupling to fibers, detectors, and potentially integrated single-photon sources. Given the maturity of silicon processing, I believe these targets are realistically achievable in the near future.
The main limitation is that silicon is an indirect-bandgap material, so deterministic single-photon sources will require heterogeneous integration of III–V emitters, color centers, or other quantum materials. In addition, two-photon absorption and free-carrier effects limit brightness and scalability in pure Si platforms. For these reasons, I expect the most powerful path forward would be a heterogeneous approach: silicon nanophotonics providing the scalable quantum optical “fabric,” augmented by specialised quantum emitters and detectors brought in from other material systems.
Q: TU/e’s model of industry – academia collaboration in photonic integration has garnered significant attention, particularly through its strong partnerships with leading Dutch high-tech companies such as ASML and Philips. In light of intensifying global competition for photonics talent, how can Europe — and the Netherlands in particular — maintain its leadership in photonic integration technologies? Furthermore, what role do interdisciplinary education and international collaboration play in developing the next generation of photonics engineers?
A: I believe the key term here is “multidisciplinary.” Photonic integrated circuit (PIC) technology is no longer confined to a single discipline or country. The supply chain encompasses multiple material platforms, both established and emerging fabrication processes, advanced packaging techniques, and design software for full photonic–electronic co-integration. No single organization, cleanroom, or nation can address this entire landscape alone. Strong collaboration across European countries and strategic partnerships beyond Europe is therefore essential to maintain a competitive, resilient, and future-ready photonics ecosystem.
From an education perspective, we need a training pipeline that produces engineers who can operate across these boundaries. The Netherlands and the EU should invest in truly interdisciplinary education that integrates photonics, electronics, packaging, software, and system engineering. This is crucial for offering a globally competitive education and talent development program. In this regard, it is worth highlighting that TU/e is already reshaping its semiconductor and photonics curriculum at both bachelor and master levels to meet exactly this emerging demand.
Q: What are your thoughts on Asia Photonics Expo 2026?
A: As an attendee of APE 2025 and a speaker at the associated Asia Photonics Conference, I view APE as a strategically important event for global photonics community, effectively bridging industry and academia. For APE 2026, I would be particularly eager to see several key elements strengthened: (1) global ecosystem that represents the full supply chain and R&D landscape from all major continents in a balanced way. Such global diversity is a key to the global collaboration; (2) strategic vision presented by leading industry and academia, to help close the gap between research innovation and commercial deployment; (3) application-themed forums to allow attendees to dive deeply into the emerging application domains, such as CPO, quantum, LiDAR, etc.
Prof. Yuqing Jiao’s Biography
Prof. Yuqing Jiao received a BSc degree from Zhejiang University, China, in 2008 with honours from the Chu Kochen Honors College. In 2010, he was awarded the Philips Brainbridge PhD Fellowship, and in 2013 he received dual Ph.D. degrees from the Eindhoven University of Technology, The Netherlands, as well as from Zhejiang University, China. After that, he continued research on integrated nanophotonics at the Institute of Photonic Integration (IPI, former COBRA Research Institute), Eindhoven University of Technology. He is currently an Associate Professor. His research interests include III-V-based integrated nanophotonics and nanoelectronics, and 3D integration technologies. He is a senior member of IEEE.
